Responsibilities:
• Experience in Virtual Verification developing Test bench, Models, Checkers and Monitors using VHDL
• Preferable candidates with DO254 based VV execution
• Development of Virtual Verification Procedures and Virtual Verification Report
• Good hands on Python/Perl/TCL
• Collaborative work applying quality standards and internal processes
• Preparation of the associated project documentation and reviews
Skills & experience:
• Must have strong experience in complete FPGA development life cycle (Technical feasibility, requirements, preliminary and detailed design, VV)
• Experience in Virtual Verification – VHDL
• Strong hands on Digital Design
• Good hands on Python/Perl/TCL
• Collaborative work applying quality standards and internal processes
• Preparation of the associated project documentation and reviews
• Must have experience to ensure the reporting progress of the project along with KPI
• Must have experience to manage risks and opportunities
• Must be rigorous, organized, autonomous and proactive, and motivated by a position within a multidisciplinary team.
• Must have demonstrated leadership skills on complex topics.